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CY7C024-55AC 参数 Datasheet PDF下载

CY7C024-55AC图片预览
型号: CY7C024-55AC
PDF下载: 下载PDF文件 查看货源
内容描述: 4K X 16/18和8K X 16/18双端口静态RAM与SEM , INT , BUSY [4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY]
分类和应用:
文件页数/大小: 21 页 / 518 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C024/024A/0241
CY7C025/0251
Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE[15]
t
DOE
Read Cycle Time
Address to Data Valid
Output Hold From Address
Change
CE LOW to Data Valid
OE LOW to Data Valid
3
10
3
10
0
15
15
15
12
12
0
0
12
10
0
10
0
30
25
0
50
35
25
20
20
0
0
20
15
0
15
0
60
35
0
25
25
35
30
30
0
0
25
15
0
20
0
70
45
3
15
0
25
35
55
35
35
0
0
35
20
0
25
3
15
10
3
15
3
20
0
55
55
15
15
3
25
13
3
20
3
25
25
25
3
35
20
3
25
35
35
3
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
7C024/024A/0241–15 7C024/024A/0241–25 7C024/024A/0241–35 7C024/024A/0241–55
7C025/0251–15
7C025/0251–25
7C025/0251–35
7C025/0251–55
Unit
Min
Max
Min
Max
Min
Max
Min
Max
t
LZOE[16, 17, 18]
OE Low to Low Z
t
HZOE[16, 17, 18]
OE HIGH to High Z
t
LZCE[16, 17, 18]
CE LOW to Low Z
t
HZCE[16, 17, 18]
CE HIGH to High Z
t
PU[18]
t
PD[18]
t
ABE[15]
Write Cycle
t
WC
t
SCE[15]
t
AW
t
HA
t
SA[15]
t
PWE
t
SD
t
HD
t
HZWE[17, 18]
t
LZWE[17, 18]
t
WDD[19]
t
DDD[19]
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
Data Setup to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read
Data Valid
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable Access Time
Notes
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OI
/I
OH
and 30 pF load capacitance.
15. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
16. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
17. Test conditions used are Load 3.
18. This parameter is guaranteed but not tested.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to
Document #: 38-06035 Rev. *D
Page 9 of 21