CY7C024/024A/0241
CY7C025/0251
Switching Characteristics
Over the Operating Range (continued)
[14]
Parameter
Busy Timing
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[21]
t
INS
t
INR
t
SOP
t
SWRD
t
SPS
t
SAA
BUSY LOW from Address
Match
BUSY HIGH from Address
Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Setup for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH
(Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or
SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
5
15
5
0
13
Note 21
15
15
12
10
10
25
15
15
15
15
5
0
20
Note 21
20
20
15
10
10
35
20
20
20
20
5
0
30
Note 21
25
25
20
15
15
55
20
20
20
20
5
0
40
Note 21
30
30
45
40
40
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
7C024/024A/0241–15 7C024/024A/0241–25 7C024/024A/0241–35 7C024/024A/0241–55
7C025/0251–15
7C025/0251–25
7C025/0251–35
7C025/0251–55
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Interrupt Timing
Semaphore Timing
Data Retention Mode
The CY7C024/024A/0241 is designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention,
within V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during
the power up and power down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (4.5V).
Timing
Data Retention Mode
V
CC
4.5V
V
CC
>
2.0V
4.5V
t
RC
V
IH
CE
V
CC
to V
CC
– 0.2V
Parameter
ICC
DR1
Test Conditions
At VCC
DR
= 2V
Max
1.5
Unit
mA
Notes
20. Test conditions used are Load 2.
21. t
BDD
is a calculated parameter and is the greater of t
WDD
–
t
PWE
(actual) or t
DDD
–
t
SD
(actual).
22. CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
Document #: 38-06035 Rev. *D
Page 10 of 21
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