CY7C024/024A/0241
CY7C025/0251
Switching Waveforms
(continued)
Figure 9. Semaphore Read After Write Timing, Either Side
t
AA
A
0
–A
2
VALID ADRESS
t
AW
SEM
t
SCE
t
SD
I/O
0
t
SA
R/W
t
SWRD
OE
WRITE CYCLE
t
SOP
READ CYCLE
t
DOE
DATA
IN
VALID
t
PWE
t
HD
DATA
OUT
VALID
t
HA
t
SOP
VALID ADRESS
t
ACE
t
OHA
Figure 10. Timing Diagram of Semaphore Contention
A
0L
–A
2L
MATCH
R/W
L
SEM
L
t
SPS
A
0R
–A
2R
MATCH
R/W
R
SEM
R
Notes
37. CE = HIGH for the duration of the above timing (both write and read cycle).
38. I/O
0R
= I/O
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH.
39. Semaphores are reset (available to both ports) at cycle start.
40. If t
SPS
is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Document #: 38-06035 Rev. *D
Page 13 of 21
CYPRESS [ CYPRESS SEMICONDUCTOR ]
