CY7C006
CY7C016
Switching Waveforms
(continued)
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)
[20, 22, 24]
t
WC
ADDRESS
t
SCE
SEM OR CE
t
SA
R/W
t
AW
t
PWE
t
HA
t
SD
DATA IN
t
HZWE
DATA OUT
DATA VALID
t
HD
t
LZWE
HIGH IMPEDANCE
C006-14
Semaphore Read After Write Timing, Either Side
[25]
t
AA
A
0
–A
2
VALID ADDRESS
t
AW
SEM
t
SCE
t
SD
I/O
0
t
SA
R/W
t
SWRD
OE
WRITE CYCLE
t
SOP
READ CYCLE
C006-15
t
OHA
VALID ADDRESS
t
ACE
t
SOP
t
HA
DATA
IN
VALID
t
PWE
t
HD
DATA
OUT
VALID
t
DOE
Notes:
24. Data I/O pins enter high-impedance when OE is held LOW during write.
25. CE = HIGH for the duration of the above timing (both write and read cycle).
9