CY7C006
CY7C016
Switching Characteristics
Over the Operating Range
[7]
7C006-15
7C016-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE[8, 9, 10]
t
HZOE[8, 9, 10]
t
LZCE[8, 9, 10]
t
HZCE[8, 9, 10]
t
PU[10]
t
PD[10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD[11]
t
HZWE[9, 10]
t
LZWE[9, 10]
t
WDD[12]
t
DDD[12]
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[14]
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
0
15
3
10
0
25
3
10
3
15
0
35
3
15
10
3
15
3
15
0
55
15
15
3
25
13
3
15
3
25
25
25
3
35
20
3
25
35
35
3
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C006-25
7C016-25
Min.
Max.
7C006-35
7C016-35
Min.
Max.
7C006-55
7C016-55
Min.
Max.
Unit
WRITE CYCLE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
3
30
25
15
12
12
0
0
12
10
0
10
3
50
30
25
20
20
0
0
20
15
0
15
3
60
35
35
30
30
0
0
25
15
0
20
3
80
60
55
45
45
0
0
40
25
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING
[13]
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Data Valid
5
0
13
Note 13
15
15
15
15
5
0
17
Note 13
20
20
20
17
5
0
25
Note 13
20
20
20
25
5
0
30
Note 13
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI
/I
OH
and 30-pF load capacitance.
8. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
9. Test conditions used are Load 3.
10. This parameter is guaranteed but not tested.
11. Must be met by the device writing to the RAM under all operating conditions.
12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
13. Test conditions used are Load 2.
14. t
BDD
is a calculated parameter and is the greater of t
WDD
– t
PWE
(actual) or t
DDD
– t
SD
(actual).
6
CYPRESS [ CYPRESS SEMICONDUCTOR ]
