CY7C006
CY7C016
Switching Waveforms
(continued)
Busy Timing Diagram No. 1 (CE Arbitration)
[29]
CE
L
Valid First:
ADDRESS
L,R
CE
L
t
PS
CE
R
t
BLC
BUSY
R
C006-19
ADDRESS MATCH
t
BHC
CE
R
Valid First:
ADDRESS
L,R
CE
R
t
PS
CE
L
t
BLC
BUSY
L
C006-20
ADDRESS MATCH
t
BHC
Busy Timing Diagram No. 2 (Address Arbitration)
[28]
Left AddressValid First:
t
RC
or t
WC
ADDRESS
L
ADDRESS MATCH
t
PS
ADDRESS
R
t
BLA
BUSY
R
C006-21
ADDRESS MISMATCH
t
BHA
Right Address Valid First:
t
RC
or t
WC
ADDRESS
R
ADDRESS MATCH
t
PS
ADDRESS
L
t
BLA
BUSY
L
C006-22
ADDRESS MISMATCH
t
BHA
Notes:
29. If t
PS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
30. t
HA
depends on which enable pin (CE
L
or R/W
L
) is deasserted first.
31. t
INS
or t
INR
depends on which enable pin (CE
L
or R/W
L
) is asserted last.
11
CYPRESS [ CYPRESS SEMICONDUCTOR ]
