CY7C006
CY7C016
Pin Configurations
(continued)
80-Pin TQFP
Top View
I/O
1L
I/O
0L
SEM
L
R/W
L
I/O
8L
OE
L
A
13L
A
12L
A
11L
CE
L
NC
A
10L
V
CC
A
9L
A
8L
A
7L
64
NC
A
6L
NC
NC
61
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
NC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
1
2
3
4
5
6
7
8
63
62
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
9
10
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
CY7C016
29
30
31
32
33
34
35
36
37
38
39
NC
A
13R
GND
A
9R
A
8R
A
7R
I/O
7R
R/W
R
SEM
R
CE
R
A
6R
NC
NC
NC
40
20
41
I/O
8R
OE
R
A
12R
A
11R
A
10R
Pin Definitions
Left Port
I/O
0L–7L(8L)
A
0L–13L
CE
L
OE
L
R/W
L
SEM
L
Right Port
I/O
0R–7R(8R)
A
0R–13R
CE
R
OE
R
R/W
R
SEM
R
Description
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O
0
pin is used when writing to a
semaphore. Semaphores are requested by writing a 0 into the respective
location.
Interrupt Flag. INT
L
is set when right port writes location 3FFE and is
cleared when left port reads location 3FFE. INT
R
is set when left port writes
location 3FFF and is cleared when right port reads location 3FFF.
Busy Flag
Master or Slave Select
Power
Ground
INT
L
INT
R
BUSY
L
M/S
V
CC
GND
BUSY
R
3
A
5R
C006-4
CYPRESS [ CYPRESS SEMICONDUCTOR ]
