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CY62148EV30LL-45ZSXI 参数 Datasheet PDF下载

CY62148EV30LL-45ZSXI图片预览
型号: CY62148EV30LL-45ZSXI
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K ×8)静态RAM [4-Mbit (512K x 8) Static RAM]
分类和应用:
文件页数/大小: 12 页 / 855 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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MoBL
®
CY62148EV30
Switching Waveforms
Figure 1. Read Cycle No. 1
(Address Transition Controlled)
t
RC
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Figure 2. Read Cycle No. 2
(OE Controlled)
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
DATA OUT
V
CC
SUPPLY
CURRENT
t
PU
50%
t
LZCE
DATA VALID
t
PD
50%
t
HZOE
t
HZCE
HIGH
IMPEDANCE
I
CC
I
SB
Figure 3. Write Cycle No. 1
(WE Controlled, OE HIGH During Write)
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA IO
NOTE 21
t
HZOE
Notes
16. Device is continuously selected. OE, CE = V
IL
.
17. WE is HIGH for read cycles.
18. Address valid before or similar to CE transition LOW.
19. Data IO is high impedance if OE = V
IH
.
20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
21. During this period, the IOs are in output state. Do not apply input signals.
t
HD
DATA VALID
Document #: 38-05576 Rev. *G
Page 6 of 12