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CY62128EV30LL-45ZXI 参数 Datasheet PDF下载

CY62128EV30LL-45ZXI图片预览
型号: CY62128EV30LL-45ZXI
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位( 128K ×8)静态RAM [1 Mbit (128K x 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 11 页 / 946 K
品牌: CYPRESS [ CYPRESS ]
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CY62128EV30 MoBL®  
Switching Waveforms  
Read Cycle 1 (Address transition controlled) [15, 16]  
tRC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE controlled) [10, 16, 17]  
ADDRESS  
t
RC  
CE  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCE  
t
PD  
ICC  
t
V
CC  
PU  
50%  
SUPPLY  
CURRENT  
50%  
ISB  
Write Cycle No. 1 (WE controlled) [10, 15, 18, 19]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
20  
DATA IO  
NOTE  
DATA VALID  
t
HZOE  
Notes:  
15. The device is continuously selected. OE, CE = V , CE = V  
.
1
IL  
2
IH  
16. WE is HIGH for read cycle.  
17. Address valid before or similar to CE transition LOW and CE transition HIGH.  
1
2
18. Data IO is high impedance if OE = V  
.
IH  
19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.  
1
2
20. During this period, the IOs are in output state. Do not apply input signals.  
Document #: 38-05579 Rev. *C  
Page 6 of 11  
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