CY62128EV30 MoBL®
Switching Characteristics (Over the Operating Range)[10, 11]
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Parameter
Read Cycle
Description
Min
45
Max
Min
Max
Unit
tRC
Read Cycle Time
55
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[12]
45
55
tOHA
tACE
tDOE
tLZOE
tHZOE
10
10
45
22
55
25
5
10
0
5
10
0
OE HIGH to High Z[12,13]
CE LOW to Low Z[12]
18
18
45
20
20
55
tLZCE
tHZCE
ns
ns
CE HIGH to High Z[12, 13]
CE LOW to Power Up
CE HIGH to Power Up
tPU
ns
ns
tPD
Write Cycle[14]
tWC
tSCE
tAW
tHA
Write Cycle Time
45
35
35
0
55
40
40
0
ns
ns
ns
ns
ns
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tSA
0
0
tPWE
tSD
35
25
0
40
25
0
ns
ns
ns
ns
ns
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z[12, 13]
WE HIGH to Low Z[12]
tHD
tHZWE
tLZWE
18
20
10
10
Notes:
11. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” on page 4.
CC(typ)
OL OH
12. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
13. t
, t
, and t
transitions are measured when the output enter a high impedance state.
HZOE HZCE
HZWE
14. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can
IL
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05579 Rev. *C
Page 5 of 11
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