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CY62128EV30LL-45ZXI 参数 Datasheet PDF下载

CY62128EV30LL-45ZXI图片预览
型号: CY62128EV30LL-45ZXI
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位( 128K ×8)静态RAM [1 Mbit (128K x 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 11 页 / 946 K
品牌: CYPRESS [ CYPRESS ]
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CY62128EV30 MoBL®  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage.......................................... > 2001V  
(MIL-STD-883, Method 3015)  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Latch up Current.....................................................> 200 mA  
Storage Temperature ..................................65°C to +150°C  
Ambient Temperature with  
Power Applied...............................................55°C to +125°C  
Operating Range  
Ambient  
[6]  
Device  
Range  
VCC  
Supply Voltage to Ground  
Potential......................................... –0.3V to VCC(max) + 0.3V  
Temperature  
CY62128EV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to  
3.6V  
DC Voltage Applied to Outputs  
in High-Z State[4, 5]......................... –0.3V to VCC(max) + 0.3V  
Auto-E  
–40°C to +125°C  
DC Input Voltage[4,5] ...................... –0.3V to VCC(max) + 0.3V  
Electrical Characteristics (Over the Operating Range)  
45 ns (Ind’l/Auto-A)  
55 ns (Auto-E)  
Parameter  
Description  
Test Conditions  
IOH = –0.1 mA  
Min Typ[3] Max  
Min Typ[3] Max Unit  
VOH  
Output HIGH Voltage  
2.0  
2.4  
2.0  
2.4  
V
V
IOH = –1.0 mA, VCC > 2.70V  
VOL  
Output LOW Voltage  
Input HIGH Voltage  
IOL = 0.1 mA  
0.4  
0.4  
0.4  
0.4  
V
V
V
IOL = 2.1 mA, VCC > 2.70V  
VCC = 2.2V to 2.7V  
VIH  
1.8  
2.2  
VCC  
+
1.8  
2.2  
VCC +  
0.3V  
0.3V  
VCC= 2.7V to 3.6V  
VCC  
+
VCC  
+
V
0.3V  
0.3V  
VIL  
Input LOW Voltage  
VCC = 2.2V to 2.7V  
VCC= 2.7V to 3.6V  
–0.3  
–0.3  
–1  
0.6  
0.8  
+1  
–0.3  
–0.3  
–4  
0.6  
0.8  
+4  
V
V
IIX  
Input Leakage Current GND < VI < VCC  
µA  
µA  
mA  
mA  
IOZ  
ICC  
Output Leakage Current GND < VO < VCC, Output Disabled  
–1  
+1  
–4  
+4  
VCC Operating Supply  
Current  
f = fmax = 1/tRC VCC = VCCmax  
11  
16  
11  
35  
IOUT = 0 mA  
CMOS levels  
f = 1 MHz  
1.3  
2.0  
1.3  
4.0  
ISB1  
Automatic CE  
Power down  
CE1 > VCC0.2V, CE2 < 0.2V  
1
1
4
4
1
1
35  
30  
µA  
VIN > VCC–0.2V, VIN < 0.2V)  
Current — CMOS Inputs f = fmax (Address and Data Only),  
f = 0 (OE and WE), VCC = 3.60V  
[7]  
ISB2  
Automatic CE  
Power down  
CE1 > VCC – 0.2V, CE2 < 0.2V  
IN > VCC – 0.2V or VIN < 0.2V,  
µA  
V
Current — CMOS Inputs f = 0, VCC = 3.60V  
Capacitance (For all packages)[8]  
Parameter Description  
Test Conditions  
Max  
10  
Unit  
CIN  
Input Capacitance  
Output Capacitance  
TA = 25°C, f = 1 MHz,  
CC = VCC(typ)  
pF  
pF  
V
COUT  
10  
Notes:  
4. V  
5. V  
= –2.0V for pulse durations less than 20 ns.  
IL(min)  
= V +0.75V for pulse durations less than 20 ns.  
IH(max)  
CC  
6. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.  
CC  
CC  
7. Only chip enables (CE and CE ) must be at CMOS level to meet the I / I spec. Other inputs can be left floating.  
1
2
SB2 CCDR  
8. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05579 Rev. *C  
Page 3 of 11  
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