Ultra37000 CPLD Family
Typical 3.3V Power Consumption (continued)
CY37064V
45
40
35
30
25
20
15
10
5
High Speed
Low Power
0
0
20
40
60
80
100
120
140
Frequency (MHz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC = 3.3V, TA = Room Temperature
CY37128V
80
70
60
50
40
30
20
10
0
H igh S peed
Low P ow er
0
20
40
60
80
100
120
140
F requ ency (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *C
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