Ultra37000 CPLD Family
Typical 3.3V Power Consumption (continued)
CY37384V
200
180
160
140
120
100
8 0
H igh S peed
Low P ow er
6 0
4 0
2 0
0
0
1 0
20
30
40
50
6 0
70
80
90
Freq uency (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
CC = 3.3V, TA = Room Temperature
V
CY37512V
2 5 0
2 0 0
1 5 0
1 0 0
5 0
H ig h S p e e d
L o w P o w e r
0
0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
CC = 3.3V, TA = Room Temperature
V
Document #: 38-03007 Rev. *C
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