Ultra37000 CPLD Family
Logic Block Diagrams
(continued)
CY37256/CY37256V (256-lead BGA)
Clock/
Input Input
1
4
4
I/O
0
−I/O
11
12 I/Os
12 I/Os
I/O
12
−I/O
23
I/O
24
−I/O
35
I/O
36
−I/O
47
I/O
48
−I/O
59
I/O
60
−I/O
71
I/O
72
−I/O
83
12 I/Os
12 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
F
LOGIC
BLOCK
G
LOGIC
BLOCK
H
96
TDO
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
4
LOGIC
BLOCK
P
LOGIC
BLOCK
O
LOGIC
BLOCK
N
LOGIC
BLOCK
M
LOGIC
BLOCK
L
LOGIC
BLOCK
K
LOGIC
BLOCK
J
LOGIC
BLOCK
I
96
12 I/Os
I/O
180
−I/O
191
12 I/Os
I/O
168
−I/O
179
12 I/Os
I/O
156
−I/O
167
12 I/Os
I/O
144
−I/O
155
12 I/Os
I/O
132
−I/O
143
12 I/Os
I/O
120
−I/O
131
12 I/Os
I/O
108
−I/O
119
12 I/Os
I/O
96
−I/O
107
12 I/Os
12 I/Os
PIM
36
16
36
16
36
16
36
16
12 I/Os
12 I/Os
I/O
84
−I/O
95
TDI
TCK
TMS
JTAG Tap
Controller
Document #: 38-03007 Rev. *D
Page 11 of 64
CYPRESS [ CYPRESS SEMICONDUCTOR ]
