Ultra37000 CPLD Family
Logic Block Diagrams
(continued)
CY37384/CY37384V (256-Lead BGA)
Clock/
Input Input
1
4
4
12 I/Os
I/O
0
−I/O
11
12 I/Os
I/O
12
−I/O
23
I/O
24
−I/O
35
12 I/Os
LOGIC
BLOCK
AA
LOGIC
BLOCK
AB
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
12 I/Os
I/O
36
−I/O
47
LOGIC
BLOCK
AE
LOGIC
BLOCK
AF
12 I/Os
I/O
48
−I/O
59
I/O
60
−I/O
71
12 I/Os
LOGIC
BLOCK
AG
LOGIC
BLOCK
AH
LOGIC
BLOCK
AI
LOGIC
BLOCK
AJ
12 I/Os
I/O
84
−I/O
95
LOGIC
BLOCK
AK
LOGIC
BLOCK
AL
TDI
TCK
TMS
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
4
LOGIC
BLOCK
BL
LOGIC
BLOCK
BK
LOGIC
BLOCK
BJ
LOGIC
BLOCK
BI
LOGIC
BLOCK
BH
LOGIC
BLOCK
BG
LOGIC
BLOCK
BF
LOGIC
BLOCK
BE
LOGIC
BLOCK
BD
LOGIC
BLOCK
BC
LOGIC
BLOCK
BB
LOGIC
BLOCK
BA
12 I/Os
I/O
96
−I/O
107
12 I/Os
I/O
120
−I/O
143
12 I/Os
I/O
108
−I/O
131
12 I/Os
I/O
96
−I/O
119
12 I/Os
I/O
132
−I/O
155
12 I/Os
I/O
168
−I/O
191
12 I/Os
I/O
156
−I/O
179
12 I/Os
I/O
144
−I/O
167
PIM
36
16
36
16
36
16
36
16
36
16
12 I/Os
I/O
72
−I/O
83
36
16
36
16
36
16
JTAG Tap
Controller
TDO
96
96
Document #: 38-03007 Rev. *D
Page 12 of 64
CYPRESS [ CYPRESS SEMICONDUCTOR ]
