Ultra37000 CPLD Family
Logic Block Diagrams
(continued)
TDI
CY37128/CY37128V (160-lead TQFP)
CLOCK
INPUTS INPUTS
1
INPUT
MACROCELL
4
4
INPUT/CLOCK
MACROCELLS
4
36
PIM
16
36
16
36
16
36
16
LOGIC
BLOCK
JTAG Tap
Controller
TDO
TCK
TMS
JTAG
EN
I/O
0
–I/O
15
16 I/Os
LOGIC
BLOCK
A
36
16
36
16
36
16
36
16
16 I/Os
I/O
112
–I/O
127
H
16 I/Os
I/O
16
–I/O
31
16 I/Os
I/O
32
–I/O
47
LOGIC
BLOCK
B
LOGIC
BLOCK
16 I/Os
I/O
96
–I/O
111
16 I/Os
I/O
80
–I/O
95
16 I/Os
I/O
64
–I/O
79
G
LOGIC
BLOCK
C
LOGIC
BLOCK
F
16 I/Os
I/O
28
–I/O
63
LOGIC
BLOCK
D
LOGIC
BLOCK
E
64
64
Clock/
Input Input
1
4
CY37192/CY37192V (160-lead TQFP)
4
10 I/Os
I/O
0
–I/O
9
10 I/Os
I/O
10
–I/O
19
10 I/Os
I/O
20
–I/O
29
10 I/Os
I/O
30
–I/O
39
10 I/Os
I/O
40
–I/O
49
10 I/Os
I/O
50
–I/O
59
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
F
60
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
4
LOGIC
BLOCK
L
LOGIC
BLOCK
K
LOGIC
BLOCK
J
LOGIC
BLOCK
I
LOGIC
BLOCK
H
LOGIC
BLOCK
G
60
10 I/Os
I/O
110
–I/O
119
10 I/Os
I/O
100
–I/O
109
10 I/Os
I/O
90
–I/O
99
10 I/Os
I/O
80
–I/O
89
10 I/Os
I/O
70
–I/O
79
10 I/Os
I/O
60
–I/O
69
PIM
36
16
36
16
36
16
TDI
TCK
TMS
JTAG Tap
Controller
TDO
Document #: 38-03007 Rev. *D
Page 10 of 64
CYPRESS [ CYPRESS SEMICONDUCTOR ]
