CY29774
AC Electrical Specifications[6] (VDD= 3.3V ± 5%, TA = –40°C to +85°C)
Parameter Description Condition
fVCO VCO Frequency
Min.
200
25
Typ.
–
Max.
500
Unit
MHz
MHz
fin
Input Frequency
÷8 Feedback
–
62.5
41.6
÷12 Feedback
16.6
12.5
8.3
6.25
4.2
0
–
÷16 Feedback
–
31.25
20.8
15.625
10.4
200
÷24 Feedback
–
÷32 Feedback
–
÷48 Feedback
–
Bypass mode (PLL_EN = 0)
–
frefDC
tr , tf
Input Duty Cycle
25
–
75
%
ns
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8V to 2.0V
÷4 Output
–
1.0
fMAX
50
25
–
125
MHz
÷8 Output
–
62.5
41.6
31.25
20.8
55
÷12 Output
÷16 Output
÷24 Output
16.6
12.5
8.3
–
–
–
DC
tr , tf
t(φ)
Output Duty Cycle
45
–
%
ns
ps
Output Rise/Fall times
0.8V to 2.4V
0.1
–
1.0
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD
does not include jitter
,
–100
–
100
tsk(O)
tsk(B)
Output-to-Output Skew
Bank-to-Bank Skew
Skew within Bank
–
–
–
–
150
150
ps
ps
Banks at same voltage,
same frequency
Banks at same voltage,
different frequency
–
–
225
Banks at different voltage
–
–
–
–
–
250
10
10
–
tPLZ, HZ
tPZL, ZH
BW
Output Disable Time
Output Enable Time
–
–
ns
ns
PLL Closed Loop Bandwidth
(–3dB)
0.5 - 1.0
MHz
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
–
–
–
–
–
–
–
–
–
–
150
300
100
150
1
ps
Multiple frequencies
tJIT(PER)
tJIT(φ)
Period Jitter
ps
ps
I/O Phase Jitter
I/O at same VDD
tLOCK
Maximum PLL Lock Time
ms
Document #: 38-07479 Rev. **
Page 6 of 9
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