CY29774
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
Input Clock * 8
Input Clock * 12
Input Clock * 16
Input Clock * 24
Input Clock * 32
Input Clock * 48
25 MHz to 62.5 MHz
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
4.2 MHz to 10.4 MHz
25 MHz to 50 MHz
÷8
16.6 MHz to 33.3 MHz
12.5 MHz to 25 MHz
8.3 MHz to 16.6 MHz
6.25 MHz to 12.5 MHz
4.2 MHz to 8.3 MHz
÷12
÷16
÷24
÷32
÷48
Table 2. Function Table (configuration controls)
Control
TCLK_SEL
VCO_SEL
PLL_EN
Default
0
1
0
0
1
TCLK0
TCLK1
VCO÷2 (high input frequency range)
VCO÷4 (low input frequency range)
Bypass mode, PLL disabled. The input clock
connects to the output dividers
PLL enabled. The VCO output
connects to the output dividers
MR#/OE
1
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the VCO running at its minimum
frequency. The device is reset by the internal
power-on reset (POR) circuitry during power-up.
Outputs enabled
Outputs enabled
CLK_STP#
1
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
Table 3. Function Table (Bank A, B and C)
VCO_SEL
SELA
QA(4:0)
÷4
SELB
QB(4:0)
÷4
SELC
QC(3:0)
÷8
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷8
÷12
÷8
÷8
÷16
÷16
÷16
÷24
Table 4. Function Table (FB_OUT)
VCO_SEL
FB_SEL1
FB_SEL0
FB_OUT
÷8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷16
÷12
÷24
÷16
÷32
÷24
÷48
Document #: 38-07479 Rev. **
Page 3 of 9
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