CY2308
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC (Top view)
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Table 1. Pin Definitions - 16 Pin SOIC
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
S1
CLKB3
CLKB4
GND
V
DD
CLKA3
CLKA4
FBK
Signal
Clock output, Bank A
Clock output, Bank A
3.3V supply
Ground
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
3.3V supply
Clock output, Bank A
Clock output, Bank A
PLL feedback input
Description
Input reference frequency, 5V tolerant input
Select Input Decoding
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Tri-State
Driven
Driven
Driven
CLOCK B1–B4
Tri-State
Tri-State
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0.
Document Number: 38-07146 Rev. *F
Page 2 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
