CY2308
Switching Characteristics for Commercial Temperature Devices
(continued)
Parameter
[8]
t
3
t
3
t
4
t
4
t
4
t
5
Name
Rise Time
(–1, –2, –3, –4)
Rise Time
(–1H, –5H)
Fall Time
(–1, –2, –3, –4)
Fall Time
(–1, –2, –3, –4)
Fall Time
(–1H, –5H)
Output to Output Skew on
same Bank
(–1, –2, –3, –4)
Test Conditions
Measured between 0.8V and 2.0V,
15-pF load
Measured between 0.8V and 2.0V,
30-pF load
Measured between 0.8V and 2.0V,
30-pF load
Measured between 0.8V and 2.0V,
15-pF load
Measured between 0.8V and 2.0V,
30-pF load
All outputs equally loaded
Min
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
Max
1.50
1.50
2.20
1.50
1.25
200
Unit
ns
ns
ns
ns
ns
ps
Output to Output Skew (–1H, All outputs equally loaded
–5H)
Output Bank A to Output
Bank B Skew (–1, –4, –5H)
Output Bank A to Output
Bank B Skew (–2, –3)
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to
FBK Rising Edge
Device to Device Skew
Output Slew Rate
Cycle to Cycle Jitter
(–1, –1H, –4, –5H)
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins
of devices
Measured between 0.8V and 2.0V on
–1H, –5H device using Test Circuit 2
Measured at 66.67 MHz, loaded
outputs,
15-pF load
Measured at 66.67 MHz, loaded
outputs,
30-pF load
Measured at 133.3 MHz, loaded
outputs,
15-pF load
t
J
Cycle to Cycle Jitter
(–2, –3)
Measured at 66.67 MHz, loaded
outputs
30-pF load
Measured at 66.67 MHz, loaded
outputs
15-pF load
t
LOCK
PLL Lock Time
Stable power supply, valid clocks
presented on REF and FBK pins
–
–
–
–
–
1
–
–
–
–
0
0
–
75
200
200
400
±250
700
ps
ps
ps
ps
ps
V/ns
200
ps
–
–
200
ps
–
–
100
ps
–
–
400
ps
–
–
400
ps
–
–
1.0
ms
Document Number: 38-07146 Rev. *F
Page 5 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
