CY2308
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay v/s Difference in Loading between FBK pin and CLKA/CLKB Pins
To close the feedback loop of the CY2308, the FBK pin can be
driven from any of the eight available output pins. The output
driving the FBK pin will be driving a total load of 7 pF plus any
additional load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the input-
output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally
loaded. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the
feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
For further information on using CY2308, refer to the appli-
cation note “CY2308: Zero Delay Buffer.”
Maximum Ratings
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Input Voltage (Except Ref) .............. –0.5V to V
DD
+ 0.5V
DC Input Voltage REF ........................................... –0.5 to 7V
Storage Temperature.................................. –65°C to +150°C
Junction Temperature...................................................150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions for CY2308SC-XX Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
IN
t
PU
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
[6]
Power-up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
0.05
Description
Min.
3.0
0
Max.
3.6
70
30
15
7
50
Unit
V
°C
pF
pF
pF
ms
Note:
6. Applies to both Ref Clock and FBK.
Document #: 38-07146 Rev. *C
Page 3 of 14
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