CY2308
Switching Characteristics for CY2308SI-XX Industrial Temperature Devices
[8]
Parameter
t
1
t
1
t
1
Name
Output Frequency
Output Frequency
Output Frequency
Duty Cycle
[7]
= t
2
÷
t
1
(–1, –2, –3, –4, –1H, –5H)
Duty Cycle
[7]
= t
2
÷
t
1
(–1, –2, –3, –4, –1H, –5H)
t
3
t
3
t
3
t
4
t
4
t
4
t
5
Rise Time
[7]
(–1, –2, –3, –4)
Rise Time
[7]
(–1, –2, –3, –4)
Rise Time
[7]
(–1H, –5H)
Fall Time
[7]
(–1, –2, –3, –4)
Fall Time
[7]
(–1, –2, –3, –4)
Fall Time
[7]
(–1H, –5H)
Test Conditions
30-pF load, All devices
20-pF load, –1H, –5H devices
[9]
15-pF load, –1, –2, –3, –4 devices
Measured at 1.4V, F
OUT
= 66.66 MHz
30-pF load
Measured at 1.4V, F
OUT
<50.0 MHz
15-pF load
Measured between 0.8V and 2.0V,
30-pF load
Measured between 0.8V and 2.0V,
15-pF load
Measured between 0.8V and 2.0V,
30-pF load
Measured between 0.8V and 2.0V,
30-pF load
Measured between 0.8V and 2.0V,
15-pF load
Measured between 0.8V and 2.0V,
30-pF load
Min.
10
10
10
40.0
45.0
50.0
50.0
Typ.
Max.
100
133.3
133.3
60.0
55.0
2.50
1.50
1.50
2.50
1.50
1.25
200
200
200
400
0
0
1
200
200
100
400
400
1.0
±250
700
Unit
MHz
MHz
MHz
%
%
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
V/ns
ps
ps
ps
ps
ps
ms
Output to Output Skew on
All outputs equally loaded
[7]
same Bank (–1, –2, –3, –4)
Output to Output Skew
(–1H, –5H)
Output Bank A to Output
Bank B Skew (–1, –4, –5H)
Output Bank A to Output
Bank B Skew (–2, –3)
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of
devices
Measured between 0.8V and 2.0V on –1H,
–5H device using Test Circuit # 2
Measured at 66.67 MHz, loaded outputs,
15-pF load
Measured at 66.67 MHz, loaded outputs,
30-pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to
FBK Rising Edge
[7]
Device to Device Skew
[7]
Output Slew Rate
[7]
Cycle to Cycle Jitter
[7]
(–1, –1H, –4, –5H)
t
J
Cycle to Cycle Jitter
[7]
(–2, –3)
Measured at 66.67 MHz, loaded outputs
30-pF load
Measured at 66.67 MHz, loaded outputs
15-pF load
t
LOCK
PLL Lock Time
[7]
Stable power supply, valid clocks
presented on REF and FBK pins
Document #: 38-07146 Rev. *C
Page 7 of 14
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