CY2308
Typical Duty Cycle
[10]
and I
DD
Trends
[11]
for CY2308–1,2,3,4
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
60
58
56
Duty Cycle (% )
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
58
56
Duty Cycle (% )
54
52
50
48
46
44
42
40
33 MHz
66 MHz
100 MH
z
133 MH
z
54
52
50
48
46
44
42
40
3
3.1
3.2
3.3
VDD (V)
3.4
3.5
3.6
33 MHz
66 MHz
100 MHz
3
3.1
3.2
3.3
VDD (V)
3.4
3.5
3.6
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
60
58
56
Duty Cycle (%)
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
60
58
56
0C
25C
70C
85C
-40C
52
50
48
46
44
42
40
20
40
60
80
Frequency (MHz)
100
120
140
Duty Cycle (%)
54
54
52
50
48
46
44
42
40
20
40
60
80
Frequency (MHz)
100
120
140
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
140
120
100
80
60
40
20
0
0
2
4
6
8
# o f Lo ad ed Out p ut s
33 M Hz
66 M Hz
1 00 M Hz
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
140
120
100
80
60
40
20
0
0
2
4
# o f Lo a de d Ou t p ut s
6
8
33 M Hz
66 M Hz
1 00 M Hz
Notes:
10. Duty Cycle is taken from typical chip measured at 1.4V.
11. I
DD
data is calculated from I
DD
= I
CORE
+ nCVf, where I
CORE
is the unloaded current.
(n = # of outputs; C = Capacitance load per output (F); V = Voltage Supply (V); f = frequency (Hz))
Document #: 38-07146 Rev. *C
Page 9 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
