Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
66BUF to PCI Buffered Clock Skew
The following figure shows the difference (skew) between the 3V33(0:5) outputs when the 66M clocks are connected
to 66IN. This offset is described in the Group Timing Relationship and Tolerances section of this data sheet. The
measurements were taken at 1.5 volts.
66BUF(0:2)
1.5-
3.5ns
PCI(0:6)
PCIF(0:2)
Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
3V66 to PCI Un-Buffered Clock Skew
The following figure show the timing relationship between 3V66_(0:5) and PCI(0:6) and PCIF(0:2) when configured to
run in the un-buffered mode.
3V66_(0:5)
1.5-
3.5ns
PCI(0:6)
PCIF(0:2)
Un-buffered Mode - 3V66_(0:5) to PCI (0:6) and PCIF(0:2) Phase Relationship
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 14 of 25
CYPRESS [ CYPRESS ]
