Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
PCI_STP# Clarification
The PCI_STP# signal is an active low input used for synchronous stopping and starting the PCI outputs while the rest
of the clock generator continues to function. The setup time for capturing PCI_STP# going low is 10 nsec (tsetup). The
PCI_F (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be
free running.
t setup
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
PCI_S
TP# Waveform Figure
PCI_STP# - De-assertion (transition from logic ‘0’ to logic ‘1’)
The de-assertion of the PCI_STP# signal will cause all PCI(0:6) and stoppable PCI_F(0:2) clocks to resume running
in a synchronous manner within 2 PCI clock periods after PCI_STP# transitions to a high level.
Note that the PCI STOP function is controlled by 2 inputs. One is the device PCI_STP# pin number 34 and the other
is SMBus byte 0 bit 3. These 2 inputs to the function are logically ANDed. If either the external pin or the internal
SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte
0 Bit 3 will return a 0 value if either of these control bits are set low thereby indicating the devices stoppable PCI
clocks are not running.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 17 of 25
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