Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
Maximum Lumped Capacitive Output
Loads
Maximum Ratings¹
Input Voltage Relative to VSS:
VSS-0.3V
Clock
Max Load
Units
pF
pF
pF
pF
Input Voltage Relative to VDDQ or AVDD: VDD+0.3V
PCI Clocks
3V66 (0,1)
66B(0:2)
48MUSB Clock
48MDOT
30
30
30
20
10
30
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-65°C to + 150°C
0°C to +85°C
3.5V
pF
pF
REF Clock
Note 1: The voltage on any input or I/o pin cannot exceed the
power pin during power-up. Power supply sequencing is NOT
required.
Table 5
Test and Measurement Setup
For Differential CPU Output Signals
The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CLK Measurement Point
TPCB
CLK
RtA1
RtB1
RLA1
RLB1
CLA
RD
Mult0
CLK Measurement Point
TPCB
CLK#
RtA2
RtB2
CLB
RLA2
RLB2
Rref
Lumped Test Load Configuration
Component
RtA1, RtA2
RLA1, RLA2
TPCB
RLB1, RLB2
RD
0.7 Volt Amplitude Value
1.0 Volt Amplitude Value
33 Ω
49.9 Ω
3” 50 ΩZ
0 Ω
∞
3” 50 ΩZ
63 Ω
∞
∞
470 Ω
RtB1, RtB2
CLA, CLB
Rref
0 Ω
2pF
33 Ω
2 pF
221 Ω w/mult0=0
475 Ω w/mult0=1
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 10 of 25
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