BCM89359 Advance Data Sheet
Power-Up Sequence and Timing
Section 19: Power-Up Sequence and
Timing
Sequencing of Reset and Regulator Control Signals
The BCM89359 has two signals that allow the host to control power consumption by enabling or disabling the
Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are
provided to indicate proper sequencing of the signals for various operational states (see Figure 42, Figure 43
on page 143, and Figure 44 and Figure 45 on page 144). The timing values indicated are minimum required
values; longer delays are also acceptable.
Description of Control Signals
•
WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON
input to control the internal BCM89359 regulators. When this pin is high, the regulators are enabled and the
WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON
and WL_REG_ON pins are low, the regulators are disabled.
•
BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM89359
regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this
pin is low and WL_REG_ON is high, the BT section is in reset.
Note:
•
The BCM89359 has an internal power-on reset (POR) circuit. The device will be held in reset for
a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least
150 ms after VDDC and VDDIO are available before initiating SDIO and PCIe accesses.
•
VBAT, VDDIO, WPT_1P8, and WPT_3P3 should not rise 10%–90% faster than 40 microseconds.
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 142
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