BCM89359 Advance Data Sheet
Sequencing of Reset and Regulator Control Signals
Control Signal Timing Diagrams
Figure 42: WLAN = ON, Bluetooth = ON
32.678 kHz
Sleep Clock
90% of VH
VBAT*
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT and VDDIO should not rise 10%–90% faster than 40 microseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high .
Figure 43: WLAN = OFF, Bluetooth = OFF
32.678 kHz
Sleep Clock
VBAT*
VDDIO
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT and VDDIO should not rise 10%–90% faster than 40 microseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 143
BROADCOM CONFIDENTIAL
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