BCM89359 Advance Data Sheet
Sequencing of Reset and Regulator Control Signals
Figure 46 shows the WLAN boot-up sequence from power-up to firmware download.
Figure 46: WLAN Boot-Up Sequence
VBAT*
VDDIO
WL_REG_ON
< 950 µs
VDDC
(from internal PMU)
< 104 ms
Internal POR
After a fixed delay following Internal POR and WL_REG_ON going high,
the device responds to host F0 (address 0x14) reads.
< 4 ms
Device requests for reference clock
8 ms
After 8 ms the reference clock is
assumed to be up. Access to PLL
registers is possible.
Host Interaction:
Host polls F0 (address 0x14) until it reads a
predefined pattern.
Host sets wake-up-wlan bit and
waits 8 ms, the maximum time for
reference clock availability.
After 8 ms, host programs PLL
registers to set crystal frequency
Chip active interrupt is asserted after the PLL locks
Host downloads
code.
*Notes:
1. VBAT and VDDIO should not rise 10%–90% faster than 40 microseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 145
BROADCOM CONFIDENTIAL
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