PRELIMINARY
CYW54907
The CYW54907 WLAN MAC supports features specified in the IEEE 802.11 base standard and amended by IEEE 802.11n/ac. The
key MAC features include:
■ Enhanced MAC for supporting IEEE 802.11ac features.
■ Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT).
■ Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP), and multiphase PSMP
operation.
■ Support for immediate ACK and Block-ACK policies.
■ Interframe space timing support, including RIFS.
■ Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges.
■ Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.
■ Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT)
generation in hardware.
■ Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management.
■ Hardware offload engine for IEEE 802.11 to IEEE 802.3 header conversion for receive packets.
■ Support for coexistence with Bluetooth and other external radios.
■ Programmable independent basic service set (IBSS) or infrastructure basic service set functionality.
■ Statistics counters for MIB support.
7.2.1 PSM
The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware in order
to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow-control operations, which are
predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general,
allowing algorithms to be optimized very late in the design process. It also allows for changes to the algorithms to track evolving IEEE
802.11 specifications.
The PSM fetches instructions from microcode memory. It uses the shared memory to obtain operands for instructions, as a data store,
and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad memory
(similar to a register bank) to store frequently accessed and temporary variables.
The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs
are colocated with the hardware functions they control and are accessed by the PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal,
or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction
literals, and the results are written into the shared memory, scratch-pad memory, or IHRs.
There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points
in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition
signals are available to the PSM without polling the IHRs) or on the results of ALU operations.
7.2.2 WEP
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform encryption and decryption as well
as MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2
AES-CCMP.
The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to use. It supplies the
keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and compute
the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames.
Document Number: 002-19312 Rev. *C
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CYPRESS [ CYPRESS ]
