PRELIMINARY
CYW54907
7. Wireless LAN Subsystem
7.1 WLAN CPU and Memory Subsystem
The CYW54907 WLAN section includes an integrated 32-bitARM Cortex-R4 processor with internal RAM and ROM. TheARM Cortex-
R4 is a low-power processor that features a low gate count, a small interrupt latency, and low-cost debug capabilities. It is intended
for deeply embedded applications that require fast interrupt response features. Delivering more than a 30% performance gain over
ARM7TDMI, the ARM Cortex-R4 implements the ARM v7-R architecture with support for the Thumb-2 instruction set.
At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/µW. It also supports integrated sleep modes.
On-chip memory for this CPU includes 576 KB of SRAM and 448 KB of ROM.
7.2 IEEE 802.11ac MAC
The CYW54907 WLAN media access controller (MAC) is designed to support high-throughput operation with low power consumption.
It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In
addition, several power-saving modes have been implemented that allow the MAC to consume very little power while maintaining
network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 11.
The following sections provide an overview of the important MAC modules.
Figure 11. WLAN MAC Architecture
Embedded CPU Interface
Host Registers, DMA Engines
TX‐FIFO
32 KB
RX‐FIFO
10 KB
PSM
PMQ
PSM
UCODE
Memory
IFS
Backoff, BTCX
WEP
TKIP, AES, WAPI
TSF
SHM
BUS
IHR
NAV
BUS
Shared Memory
6 KB
RXE
RX A‐MPDU
TXE
TX A‐MPDU
EXT‐ IHR
MAC‐PHY Interface
Document Number: 002-19312 Rev. *C
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