ADVANCE
CYW43570
12. Pin Diagram and Signal Descriptions
12.1 Ball Maps
Figure 22 and Figure 23 show the FCBGA ball map.
Figure 22. FCBGA Ball Map, 10 mm × 10 mm Array, 242 Balls (Top View, 1 of 2)
1
2
3
4
5
6
7
8
9
10
11
12
PCIE_RXTX_
AVDD1P2
PCIE_REFCL PCIE_REFCL
A
B
VSSC
GPIO_5
PCIE_TESTP PCIE_TESTN
GPIO_2
PCIE_RDP0 PCIE_RDN0 PCIE_TDP0 PCIE_TDN0
PCIE_AVSS
KP
KN
BT_USB_DN
VSSC
GPIO_6
PCIE_AVSS
C
D
E
F
BT_USB_DP BT_SF_CLK
BT_SF_CS_L
BT_UART_R BT_UART_C
BT_I2S_WS OTP_VDD33
BT_SF_MISO
LPO_IN
VSSC
VSSC
XD
TS_L
BT_UART_T
XD
G
H
J
BT_I2S_CLK
GPIO_4
BT_GPIO_4
BT_SF_MOSI
BT_I2S_DO
BT_I2S_DI
VSSC
VSSC
VDDC
BT_DEV_WA BT_HOST_W
KE AKE
BT_CLK_RE
Q
BT_IFVDD1P BT_VCOVDD
1P2
AVDD_BBPL
L
K
L
BTRGND
BTRGND
BTRGND
BT_VDDO
BTRGND
BTRGND
2
BT_LNAVDD BT_PLLVDD1
AVSS_BBPLL
VDDC
1P2
P2
M
N
P
R
T
BTRGND
BTRGND
BTRGND
BTRGND
BTRGND
RGND
BT_VDDC
BT_VDDC
BTRGND
BT_RF
BT_PAVDD2
P5
VDDC
VSSC
VDDC
VSSC
BTRGND
BTRGND
RGND
BTRGND
RGND
BTRGND
WRF_RFIN_2
G_CORE0
RGND
U
V
W
Y
RGND
RGND
RGND
WRF_RFOUT
_2G_CORE0
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
WRF_TSSI_A
_CORE0
WRF_GPIO_ WRF_PFD_G WRF_CP_GN WRF_MMD_
OUT_CORE0
RGND
ND1P2
D1P2
GND1P2
WRF_PA2G_
VBAT_VDD3
P3_CORE0
RGND
RGND
RGND
WRF_PADRV
AA _VBAT_VDD
3P3_CORE0
WRF_PA5G_
AB VBAT_VDD3
P3_CORE0
RGND
RGND
RGND
RGND
RGND
RGND
RGND
WRF_BUCK_
VDD1P5_CO
RE0
WRF_SYNTH
_VBAT_VDD
3P3
WRF_RFOUT
_5G_CORE0
WRF_RFIN_5
G_CORE0
WRF_PFD_V WRF_MMD_
WRF_RFIN_2
G_CORE1
AC
RGND
RGND
RGND
RGND
RGND
DD1P2
VDD1P2
1
2
3
4
5
6
7
8
9
10
11
12
Document Number: 002-15054 Rev. *I
Page 46 of 94
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