ADVANCE
CYW43570
7. Bluetooth Peripheral Transport Unit
7.1 SPI/UART Transport Detection
The BT_HOST_WAKE pin is also used for BT transport detection. The transport detection occurs during the power-up sequence. It
selects either UART or SPI transport operation based on the following pin states:
■ If the BT_HOST_WAKE pin is pulled low by an external pull-down during power-up, it selects the SPI transport interface.
■ If the BT_HOST_WAKE pin is not pulled low externally during power-up, then the default internal pull-up is detected as a high and
it selects the UART transport interface.
7.2 PCM Interface
The CYW43570 supports two independent PCM interfaces that share pins with the serial flash interfaces.
Table 6 shows PCM signal mapping used in this data sheet:
Table 6. PCM-to-Serial Flash Interface Mapping
PCM Interface Pins
Serial Flash Interface Pins
BT_PCM_CLK
BT_PCM_IN
BT_SF_CLK
BT_SF_MISO
BT_SF_MOSI
BT_SF_CS_L
BT_PCM_OUT
BT_PCM_SYNC
The PCM Interface on the CYW43570 can connect to linear PCM Codec devices in master or slave mode. In master mode, the
CYW43570 generates the BT_PCM_CLK and BT_PCM_SYNC signals, and in slave mode, these signals are provided by another
master on the PCM interface and are inputs to the CYW43570.
The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.
7.2.1 Slot Mapping
The CYW43570 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample
interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or
1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM
data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow
other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM
clock during the last bit of the slot.
7.2.2 Frame Synchronization
The CYW43570 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization
mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is
synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the
first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization
signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.
7.2.3 Data Formatting
The CYW43570 may be configured to generate and accept several different data formats. For conventional narrow band speech
mode, the CYW43570 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support
various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit,
or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.
Document Number: 002-15054 Rev. *I
Page 24 of 94
CYPRESS [ CYPRESS ]
