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BCM43570KFFBG 参数 Datasheet PDF下载

BCM43570KFFBG图片预览
型号: BCM43570KFFBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip 5G WiFi IEEE 802.11ac 2×2MAC/Baseband/Radio with IntegratedBluetooth 4.1 and EDR]
分类和应用:
文件页数/大小: 93 页 / 8056 K
品牌: CYPRESS [ CYPRESS ]
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ADVANCE  
CYW43570  
7.2.4 Wideband Speech Support  
When the host encodes wideband speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM  
bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-  
bit samples, resulting in a 64 kbps bit rate. The CYW43570 also supports slave transparent mode using a proprietary rate-matching  
scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 kbps rate) is transferred over the PCM bus.  
7.2.5 Burst PCM Mode  
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and  
save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with  
an HCI command from the host.  
7.2.6 PCM Interface Timing  
Short Frame Sync, Master Mode  
Figure 8. PCM Timing Diagram (Short Frame Sync, Master Mode)  
1
2
3
BT_PCM_CLK  
4
BT_PCM_SYNC  
BT_PCM_OUT  
8
HIGH IMPEDANCE  
7
5
6
BT_PCM_IN  
Table 7. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)  
Reference Characteristics Minimum  
PCM bit clock frequency  
Typical  
Maximum  
Unit  
MHz  
1
12  
2
3
4
5
6
7
8
PCM bit clock LOW  
PCM bit clock HIGH  
BT_PCM_SYNC delay  
BT_PCM_OUT delay  
BT_PCM_IN setup  
BT_PCM_IN hold  
41  
41  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25  
25  
0
8
8
Delay from rising edge of BT_PCM_BCLK  
during last bit period to BT_PCM_OUT  
becoming high impedance.  
0
25  
Document Number: 002-15054 Rev. *I  
Page 25 of 94  
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