ADVANCE
CYW43570
Long Frame Sync, Slave Mode
Figure 11. PCM Timing Diagram (Long Frame Sync, Slave Mode)
1
2
3
BT_PCM_CLK
4
5
BT_PCM_SYNC
9
Bit 0
Bit 0
HIGH IMPEDANCE
BT_PCM_OUT
BT_PCM_IN
Bit 1
6
7
8
Bit 1
Table 10. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
Reference Characteristics Minimum
PCM bit clock frequency
Typical
Maximum
Unit
MHz
1
–
–
–
–
–
–
–
–
–
–
12
–
2
3
4
5
6
7
8
9
PCM bit clock LOW
PCM bit clock HIGH
BT_PCM_SYNC setup
BT_PCM_SYNC hold
BT_PCM_OUT delay
BT_PCM_IN setup
BT_PCM_IN hold
41
41
8
ns
ns
ns
ns
ns
ns
ns
ns
–
–
8
–
0
25
–
8
8
–
Delay from rising edge of BT_PCM_CLK
during last bit period to BT_PCM_OUT
becoming high impedance.
0
25
Document Number: 002-15054 Rev. *I
Page 28 of 94
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