ADVANCE
CYW43570
Long Frame Sync, Master Mode
Figure 10. PCM Timing Diagram (Long Frame Sync, Master Mode)
1
2
3
BT_PCM_CLK
4
BT_PCM_SYNC
BT_PCM_OUT
8
HIGH IMPEDANCE
7
Bit 0
Bit 0
Bit 1
Bit 1
5
6
BT_PCM_IN
Table 9. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Reference Characteristics Minimum
PCM bit clock frequency
Typical
Maximum
Unit
MHz
1
2
3
4
5
6
7
8
–
–
–
–
–
–
–
–
–
12
–
PCM bit clock LOW
PCM bit clock HIGH
BT_PCM_SYNC delay
BT_PCM_OUT delay
BT_PCM_IN setup
BT_PCM_IN hold
41
41
0
ns
ns
ns
ns
ns
ns
ns
–
25
25
–
0
8
8
–
Delay from rising edge of BT_PCM_CLK
during last bit period to BT_PCM_OUT
becoming high impedance.
0
25
Document Number: 002-15054 Rev. *I
Page 27 of 94