BCM4354 Data Sheet
Signal Descriptions
Table 22: WLBGA Signal Descriptions
Type Description
Ball#
Signal Name
BT_UART_TXD
J5
O
UART serial output. Serial data output for the HCI
UART interface.
Bluetooth/FM I2S
I2S clock, can be master (output) or slave (input).
I2S data output
J6
BT_I2S_CLK
I/O
I/O
I/O
I/O
G6
G5
L6
BT_I2S_DO
BT_I2S_DI
BT_I2S_WS
I2S data input
I2S WS; can be master (output) or slave (input).
Bluetooth GPIO
–
BT_GPIO_2
I/O Bluetooth general-purpose I/O
I/O Bluetooth general-purpose I/O
I/O Bluetooth general-purpose I/O
I/O Bluetooth general-purpose I/O
–
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5
K4
–
Miscellaneous
A10
WL_REG_ON
I
Used by PMU to power up or power down the internal
BCM4354 regulators used by the WLAN section.
Also, when deasserted, this pin holds the WLAN
section in reset. This pin has an internal 200 kΩ pull-
down resistor that is enabled by default. It can be
disabled through programming.
D10
BT_REG_ON
I
Used by PMU to power up or power down the internal
BCM4354 regulators used by the Bluetooth/FM
section. Also, when deasserted, this pin holds the
Bluetooth/FM section in reset. This pin has an internal
200 kΩ pull-down resistor that is enabled by default. It
can be disabled through programming.
L4
J3
BT_DEV_WAKE
BT_HOST_WAKE
I/O Bluetooth DEV_WAKE
I/O Bluetooth HOST_WAKE
Integrated Voltage Regulators
B11
B12
A11
SR_VDDBATA5V
SR_VDDBATP5V
SR_VLX
I
I
Quiet VBAT
Power VBAT
O
CBuck switching regulator output. Refer to Table 43
on page 158 for details of the inductor and capacitor
required on this output.
C12
E12
P11
N10
D11
C11
D12
E11
LDO_VDD1P5
I
LNLDO input
LDO_VDDBAT5V
WRF_XTAL_VDD1P5
WRF_XTAL_VDD1P2
VOUT_LNLDO
I
LDO VBAT.
I
XTAL LDO input (1.35V)
XTAL LDO output (1.2V)
Output of LNLDO
Output of core LDO
Output of BT LDO
Output of 3.3V LDO
O
O
O
O
O
VOUT_CLDO
VOUT_BTLDO2P5
VOUT_LDO3P3_B
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 115
BROADCOM CONFIDENTIAL
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