BCM4354 Data Sheet
WLAN/BT GPIO Signals and Strapping Options
WLAN/BT GPIO Signals and Strapping Options
The pins listed in Table 23 and Table 24 are sampled at power-on reset (POR) to determine the various
operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR.
After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table.
Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default
mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kꢀ
resistor or less.
Note: Refer to the reference board schematics for more information.
Table 23: WLAN GPIO Functions and Strapping Options
Pin Name
Default Function Description
GPIO_4
0
1: SPROM is present
0: SPROM is absent (default). Applicable in PCIe Host mode.
Note: In SDIO Host mode, sdioPadVddio is 3.3V while set to 1, and 1.8V
while set to 0.
GPIO_5
0
0: sflash absent (default)
1: sflash present
GPIO_[10, 9, 8]
GPIO_12
[0,0,0]
1
Host interface selection: see Table 25.
1 = HTAvailable (default)
0 = ResourceModeInit is ALPAvailable. On PCBs, use a pull-down and tie
to ALP clock mode.
Table 24: BT GPIO Functions and Strapping Options
Default
Function Description
Pin Name
BT_GPIO4
0
1: BT Serial Flash is present.
0: BT Serial Flash is absent (default)
Table 25: GPIO_[10, 9, 8] Host Interface Selection
GPIO_[10, 9, 8]
Bit Setting
WLAN Host Interface Mode
Bluetooth Mode
000
010
011
SDIO
BTUART or BTUSB;
BT tPorts stand-alone.
HSIC_30D
PCIE
BTUART or BTUSB;
BT tPorts stand-alone
BTUART or BTUSB;
BT tPorts stand-alone
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 119
BROADCOM CONFIDENTIAL
CYPRESS [ CYPRESS ]
