BCM4354 Data Sheet
Signal Descriptions
Table 22: WLBGA Signal Descriptions
Type Description
Ball#
Signal Name
RF Switch Control Lines
R7
RF_SW_CTRL_0
RF_SW_CTRL_1
RF_SW_CTRL_2
RF_SW_CTRL_3
RF_SW_CTRL_4
RF_SW_CTRL_5
RF_SW_CTRL_6
RF_SW_CTRL_7
RF_SW_CTRL_8
RF_SW_CTRL_9
RF_SW_CTRL_10
RF_SW_CTRL_11
RF_SW_CTRL_12
RF_SW_CTRL_13
RF_SW_CTRL_14
RF_SW_CTRL_15
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Programmable RF switch control lines. The control
lines are programmable via the driver and NVRAM
file.
N8
P9
N7
N5
P7
P5
M8
K12
J11
M12
L9
J9
K10
M10
L8
WLAN PCI Express Interface
D5
PCIE_CLKREQ_L
OD PCIe clock request signal which indicates when the
REFCLK to the PCIe interface can be gated.
1 = the clock can be gated
0 = the clock is required
C4
PCIE_PERST_L
I (PU) PCIe System Reset. This input is the PCIe reset as
defined in the PCIe base specification version 1.1.
B1
C1
A5
A4
A3
A2
C5
PCIE_RDN0
I
I
Receiver differential pair (×1 lane)
PCIE_RDP0
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_TDN0
I
PCIE Differential Clock inputs (negative and positive).
100 MHz differential.
I
O
O
Transmitter differential pair (×1 lane)
PCIE_TDP0
PCIE_PME_L
OD PCI power management event output. Used to
request a change in the device or system power state.
The assertion and deassertion of this signal is
asynchronous to the PCIe reference clock. This signal
has an open-drain output structure, as per the PCI
Bus Local Bus Specification, revision 2.3.
C3
C2
PCIE_TESTP
PCIE_TESTN
–
–
PCIe test pin
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 112
BROADCOM CONFIDENTIAL
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