CYW4343X
Table 23. WLCSP Signal Descriptions (Cont.)
WLCSP Bump Type Description or Instruction
Signal Name
Bluetooth/FM I2S
I2S or PCM clock; can be master (output) or slave (input)
I2S or PCM data input
BT_I2S_CLK or BT_PCM_CLK
BT_I2S_DI or BT_PCM_IN
15
23
24
18
I/O
I
I2S or PCM data output
BT_I2S_DO or BT_PCM_OUT
BT_I2S_WS or BT_PCM_SYNC
O
I/O
I2S WS or PCM SYNC; can be master (output) or slave
(input)
Miscellaneous
WL_REG_ON
BT_REG_ON
148
149
I
Used by PMU to power up or power down the internal
regulators used by the WLAN section. Also, when
deasserted, this pin holds the WLAN section in reset. This
pin has an internal 200 k pull-down resistor that is enabled
by default. It can be disabled through programming.
I
Used by PMU to power up or power down the internal
regulators used by the Bluetooth/FM section. Also, when
deasserted, this pin holds the Bluetooth/FM section in reset.
This pin has an internal 200 k pull-down resistor that is
enabled by default. It can be disabled through programming.
WPT_3P3
WPT_1P8
GPIO_0
146
145
100
N/A
N/A
I/O
Not used. Do not connect to this pin.
Not used. Do not connect to this pin.
Programmable GPIO pin. This pin becomes an output pin
when it is used as WLAN_HOST_WAKE/out-of-band signal.
GPIO_1
101
97
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
VDDIO
GPIO_2
GPIO_3
98
GPIO_4
91
GPIO_5
94
GPIO_6
89
GPIO_7
87
GPIO_8
84
GPIO_9
82
GPIO_10
83
GPIO_11
81
GPIO_12
80
GPIO_13
119
105
109
110
113
116
117
GPIO_14
GPIO_15
PACKAGEOPTION_0
PACKAGEOPTION_1
PACKAGEOPTION_2
JTAG_SEL
I
Ground
I
Ground
I
JTAG select. Connect to ground.
Integrated Voltage Regulators
SR_VDDBAT5V
SR_VLX
129, 130, 132
126, 127, 128
I
SR VBAT input power supply
O
CBUCK switching regulator output. See Table 42 on
page 107 for details of the inductor and capacitor required on
this output.
LDO_VDDBAT5V
LDO_VDD1P5
VOUT_LNLDO
VOUT_CLDO
141, 147
133, 135
138
I
LDO VBAT
I
LNLDO input
O
O
Output of low-noise LDO (LNLDO)
Output of core LDO
134, 136
Document No. 002-14797 Rev. *H
Page 84 of 128
CYPRESS [ CYPRESS ]
