CYW4343X
Table 23. WLCSP Signal Descriptions (Cont.)
WLCSP Bump Type Description or Instruction
Signal Name
Ground
BT_DVSS
50
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I
Bluetooth digital ground
BT_LNAVSS
BT_PAVSS
BT_PLLVSS
BT_VCOVSS
55
Bluetooth LNA ground
Bluetooth PA ground
Bluetooth PLL ground
Bluetooth VCO ground
FM DAC analog ground
FM IF-block ground
FM PLL analog ground
FM RF ground
35
56
58
FM_DAC_AVSS
FM_IFVSS
FM_PLLAVSS
FM_RFVSS
FM_VCOVSS
PLL_VSSC
PMU_AVSS
SR_PVSS
38
47
39
46
42
FM VCO ground
151
131
123, 124
PLL core ground
Quiet ground
I
Switcher-power ground
Core ground for WLAN and BT
VSSC
21, 25, 27, 29, 30,
32, 33, 36, 78, 85,
88, 90, 92, 102,
106, 111, 121, 125,
142
I
WRF_AFE_GND
60
I
I
I
I
I
I
AFE ground
WRF_RX2G_GND
WRF_GENERAL_GND
WRF_PA_GND3P3
WRF_VCO_GND
62
2.4 GHz internal LNA ground
Miscellaneous RF ground
2.4 GHz PA ground
VCO/LO generator ground
XTAL ground
64
65, 69
66
WRF_XTAL_GND1P2
72
14.9 WLAN GPIO Signals and Strapping Options
The pins listed in Table 24 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few
milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative
function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor
that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground using
a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 24. GPIO Functions and Strapping Options
Pin Name
WLBGA Pin # Default
L7
Function
Description
SDIO_DATA_2
1
WLAN host interface
select
This pin selects the WLAN host interface mode. The
default is SDIO. For gSPI, pull this pin low.
14.10 Chip Debug Options
The chip can be accessed for debugging via the JTAG interface, multiplexed on the SDIO_DATA_0 through SDIO_DATA_3 (and
SDIO_CLK) I/O or the Bluetooth PCM I/O depending on the bootstrap state of GPIO_1 and GPIO_2.
Table 25 shows the debug options of the device.
Table 25. Chip Debug Options
BT PCM I/O Pad
Function
JTAG_SEL
GPIO_2
GPIO_1
Function
Normal mode
JTAG over SDIO
SDIO I/O Pad Function
0
0
0
0
0
1
SDIO
JTAG
BT PCM
BT PCM
Document No. 002-14797 Rev. *H
Page 86 of 128
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