CYW4343X
14. Pinout and Signal Descriptions
14.1 Ball Map
Figure 48 on page 65 shows the 63-ball WLBGA ball map.Figure 47 shows the 74-ball WLBGA ball map. Figure 49 on page 66 shows the 153-bump
WLCSP.
Figure 47. 74-Ball WLBGA Ball Map (Bottom View)
A
B
C
D
E
F
G
H
J
K
L
M
BT_UART_ BT_DEV_ BT_HOST_
BT_VCO_V
DD
WLRF_2G_ WLRF_2G_
WLRF_PA_
VDD
FM_RF_IN
BT_IF_VDD BT_PAVDD
1
2
3
4
5
6
7
1
2
3
4
5
6
7
RXD
WAKE
WAKE
eLG
RF
WLRF_GE
NERAL_GN
D
WLRF_VD
D_
1P35
BT_UART_ BT_UART_
FM_RF_VD BTFM_PLL BTFM_PLL
WLRF_LNA
_GND
WLRF_PA_
GND
FM_OUT1 FM_OUT2
BT_IF_VSS
TXD
CTS_N
D
_VDD
_VSS
WLRF_XTA
L_
VDD1P2
BT_I2S_
WS
BT_UART_
VDDC
FM_RF_VS
S
BT_VCO_V WLRF_GPI
WLRF_VC
O_GND
BT_I2S_DO
RTS_N
SS
O
BT_I2S_CL BT_PCM_O BT_PCM_I
UT
WLRF_AFE
_GND
WLRF_XTA WLRF_XTA
VSSC
BT_GPIO_3
VDDC
GPIO_3
GPIO_4
K
N
L_GND
L_XOP
BT_PCM_C BT_PCM_S SYS_VDDI
WLRF_XTA
L_XON
WPT_1P8 WPT_3P3
LPO_IN BT_GPIO_4 BT_GPIO_5
VSSC
GPIO_2
LK
YNC
O
PMU_AVS VOUT_CLD VOUT_LNL BT_REG_O WCC_VDDI WL_REG_
SDIO_DAT
A_0
SR_VLX
GPIO_1
GPIO_0
SDIO_CMD CLK_REQ
S
O
DO
N
O
ON
SR_VDDB LDO_VDD1
LDO_VDD
BAT5V
SDIO_DAT SDIO_DAT
SDIO_DAT
SDIO_CLK
A_2
SR_PVSS
VOUT_3P3
AT5V
P5
A_1
A_3
A
B
C
D
E
F
G
H
J
K
L
M
Document No. 002-14797 Rev. *H
Page 64 of 128
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