CYW4343X
Figure 48. 63-Ball WLBGA Ball Map (Bottom View)
A
B
C
D
E
F
G
H
J
K
L
M
BT_UART_ BT_DEV_ BT_HOST_
RXD WAKE WAKE
BT_VCO_
VDD
BT_IF_
VDD
WLRF_
2G_eLG
WLRF_
2G_RF
WLRF_
PA_VDD
FM_RF_IN
BT_PAVDD
1
2
3
4
5
6
7
1
2
3
4
5
6
7
WLRF_
GENERAL_
GND
WLRF_VD
D_
1P35
BT_UART_ BT_UART_
TXD CTS_N
FM_RF_
VDD
BTFM_
PLL_VDD PLL_VSS
BTFM_
WLRF_
LNA_GND
WLRF_PA_
GND
FM_OUT1 FM_OUT2
BT_IF_VSS
BT_UART_
VDDC
FM_RF_VS
S
BT_VCO_V WLRF_GPI
WLRF_VC WLRF_XTA
O_GND L_VDD1P2
RTS_N
SS
O
BT_PCM_ BT_PCM_I
OUT
WLRF_AFE
_GND
WLRF_XTA WLRF_XTA
VSSC
VDDC
N
L_GND
L_XOP
BT_PCM_ BT_PCM_
WLRF_XTA
L_XON
LPO_IN
VSSC
GPIO_2
CLK
SYNC
PMU_AVS VOUT_CLD VOUT_LNL BT_REG_O WCC_VDDI WL_REG_
SDIO_
DATA_0
SR_VLX
GPIO_1
GPIO_0
SDIO_CMD CLK_REQ
S
O
DO
N
O
ON
SR_
VDDBAT5V
LDO_VDD1
P5
LDO_
VDDBAT5V
SDIO_
DATA_1
SDIO_
DATA_3
SDIO_
SR_PVSS
VOUT_3P3
SDIO_CLK
DATA_2
A
B
C
D
E
F
G
H
J
K
L
M
Document No. 002-14797 Rev. *H
Page 65 of 128
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