CYW4343X
Figure 45. 4-Wire Coexistence Interface to an LTE IC
GPIO_1
WLAN Priority
WLAN
BT/FM
GPIO_2
GPIO_3
GPIO_4
LTE_Frame_Sync
Coexistence
Interface
LTE_RX
LTE_TX
CYW4343X
LTE/IC
Note: OR’ing to generate WCN_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by
setting the GPIO mask registers appropriately.
12.5 JTAG Interface
The CYW4343X supports the IEEE 1149.1 JTAG boundary scan standard over SDIO for performing device package and PCB
assembly testing during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary
debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins
by means of test points or a header on all PCB designs.
12.6 UART Interface
One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI
pin, and UART_TX is available on the JTAG_TDO pin.
The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the
CYW4343X to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It
is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction.
Document No. 002-14797 Rev. *H
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