CYW4343X
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Signal dependent mono/stereo blending
12. CPU and Global Functions
12.1 WLAN CPU and Memory Subsystem
The CYW4343X includes an integrated ARM Cortex-M3 processor with internal RAM and ROM. The ARM Cortex-M3 processor is a
low-power processor that features low gate count, low interrupt latency, and low-cost debugging. It is intended for deeply embedded
applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for the
Thumb-2 instruction set. ARM Cortex-M3 provides a 30% performance gain over ARM7TDMI.
At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/µW. It supports integrated sleep modes.
ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced
silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM Cor-
tex-M3 supports extensive debug features including real-time tracing of program execution.
On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM.
12.2 One-Time Programmable Memory
Various hardware configuration parameters may be stored in an internal 4096-bit One-Time Programmable (OTP) memory, which is
read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and the
MAC address, can be stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.
The entire OTP array can be programmed in a single write cycle using a utility provided with the Broadcom WLAN manufacturing
test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0
state can be altered during each programming cycle.
Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with
the reference board design package. Documentation on the OTP development process is available on the Broadcom customer sup-
port portal (http://www.broadcom.com/support).
12.3 GPIO Interface
Five general purpose I/O (GPIO) pins are available on the CYW4343X that can be used to connect to various external devices.
GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.
They can also be programmed to have internal pull-up or pull-down resistors.
GPIO_0 is normally used as a WL_HOST_WAKE signal.
The CYW4343X supports a 2-wire coexistence configuration using GPIO_1 and GPIO_2. The CYW4343X supports 2-wire, 3-wire,
and 4-wire coexistence configurations using GPIO_1 through GPIO_4. The signal functions of GPIO_1 through GPIO_4 are pro-
grammable to support the three coexistence configurations.
12.4 External Coexistence Interface
The CYW4343X supports a 2-wire, 3-wire, and 4-wire coexistence interfaceinterfaces to enable signaling between the device and an
external colocated wireless device in order to manage wireless medium sharing for optimal performance. The external colocated
device can be any of the following ICs: GPS, WiMAX, LTE, or UWB. An LTE IC is used in this section for illustration.
12.4.1 2-Wire Coexistence
Figure 43 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure:
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GPIO_1: WLAN_SECI_TX output to an LTE IC.
GPIO_2: WLAN_SECI_RX input from an LTE IC.
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Document No. 002-14797 Rev. *H
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