PRELIMINARY
CYW43438
14.5 WLAN GPIO Signals and Strapping Options
The pins listed in Table 18 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few
milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative
function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor
that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground using
a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 18. GPIO Functions and Strapping Options
Pin Name
WLBGA Pin # Default
L7
Function
Description
WLAN host interface
select
This pin selects the WLAN host interface mode. The
default is SDIO. For gSPI, pull this pin low.
SDIO_DATA_2
1
14.6 Chip Debug Options
The chip can be accessed for debugging via the JTAG interface, multiplexed on the SDIO_DATA_0 through SDIO_DATA_3 (and
SDIO_CLK) I/O or the Bluetooth PCM I/O depending on the bootstrap state of GPIO_1 and GPIO_2.
Table 19 shows the debug options of the device.
Table 19. Chip Debug Options
JTAG_SEL
GPIO_2
GPIO_1
Function
Normal mode
SDIO I/O Pad Function BT PCM I/O Pad Function
0
0
0
0
0
0
1
1
0
1
0
1
SDIO
JTAG
SDIO
BT PCM
BT PCM
JTAG
JTAG over SDIO
JTAG over BT PCM
SWD over GPIO_1/GPIO_2 SDIO
BT PCM
Document Number: 002-14796 Rev. *K
Page 62 of 101
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