PRELIMINARY
CYW43438
14.4 Signal Descriptions
Table 17 provides the WLBGA package signal descriptions.
Table 17. WLBGA Signal Descriptions
WLBGA
Signal Name
Type
Description
Ball
RF Signal Interface
WLRF_2G_RF
K1
O
2.4 GHz BT and WLAN RF output port
SDIO Bus Interface
SDIO clock input
SDIO_CLK
M7
L6
K6
H7
L7
J7
I
SDIO_CMD
I/O
I/O
I/O
I/O
I/O
SDIO command line
SDIO data line 0
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SDIO data line 1.
SDIO data line 2. Also used as a strapping option (see Table 20).
SDIO data line 3
Note: Per Section 6 of the SDIO specification, 10 to 100 kΩ pull-ups are required on the four DATA lines and the CMD line. This
requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host
pull-ups.
WLAN GPIO Interface
WLRF_GPIO
J3
I/O
Test pin. Not connected in normal operation.
Clocks
WLRF_XTAL_XON
WLRF_XTAL_XOP
M5
M4
O
I
XTAL oscillator output
XTAL oscillator input
External system clock request—Used when the system clock is not provided
by a dedicated crystal (for example, when a shared TCXO is used). Asserted
to indicate to the host that the clock is required. Shared by BT, and WLAN.
CLK_REQ
LPO_IN
M6
F5
O
I
External sleep clock input (32.768 kHz). If an external 32.768 kHz clock
cannot be provided, pull this pin low. However, BLE will be always on and
cannot go to deep sleep.
FM Receiver
FM_OUT1
FM_OUT2
FM_RF_IN
FM_RF_VDD
C2
D2
E1
E2
O
O
I
FM analog output 1
FM analog output 2
FM radio antenna port
I
FM power supply
Bluetooth PCM
BT_PCM_CLK or BT_I2S_CLK
BT_PCM_IN or BT_I2S_DI
A5
C4
B4
B5
I/O
I
PCM or I2S clock; can be master (output) or slave (input)
PCM or I2S data input sensing
PCM or I2S data output
BT_PCM_OUT or BT_I2S_DO
BT_PCM_SYNC or BT_I2S_WS
O
I/O
PCM SYNC or I2S_WS; can be master (output) or slave (input)
Document Number: 002-14796 Rev. *K
Page 59 of 101
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