PRELIMINARY
CYW43438
Table 7. gSPI Registers (Cont.)
Address Register
Bit
0
Access
R
Default
Description
1
F1 enabled
x000C, x000D F1 info. register
x000E, x000F F2 info. register
1
R
0
12'h40
1
F1 ready for data transfer
F1 maximum packet size
F2 enabled
13:2
0
R/U
R/U
R
1
0
F2 ready for data transfer
F2 maximum packet size
15:2
R/U
14'h800
This register contains a predefined pattern, which the
host can read to determine if the gSPI interface is
working properly.
Test-Read only
x0014 to x0017
32'hFEEDB
EAD
31:0
31:0
R
register
This is a dummy register where the host can write some
pattern and read it back to determine if the gSPI interface
is working properly.
32'h000000
00
x0018 to x001B Test–R/W register
R/W/U
Individual response delays for F0, F1, F2, and F3. The
value of the registers is the number of byte delays that
are introduced before data is shifted out of the gSPI
interface during host reads.
0x1D = 4,
other
registers = 0
Response delay
x001C to x001F
7:0
R/W
registers
Figure 15 shows the WLAN boot-up sequence from power-up to firmware download, including the initial device power-on reset (POR)
evoked by the WL_REG_ON signal. After initial power-up, the WL_REG_ON signal can be held low to disable the CYW43438 or
pulsed low to induce a subsequent reset.
Note: The CYW43438 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 3 ms after
VDDC and VDDIO have both passed the 0.6V threshold.
Document Number: 002-14796 Rev. *K
Page 23 of 101
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