PRELIMINARY
CYW43438
4.2.3 Boot-Up Sequence
After power-up, the gSPI host needs to wait 50 ms for the device to be out of reset. For this, the host needs to poll with a read command
to F0 address 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register
content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wake-up WLAN bit (F0 reg
0x00 bit 7). Wake-up WLAN turns the PLL on; however, the PLL doesn't lock until the host programs the PLL registers to set the crystal
frequency.
For the first time after power-up, the host needs to wait for the availability of the low-power clock inside the device. Once it is available,
the host needs to write to a PMU register to set the crystal frequency. This will turn on the PLL. After the PLL is locked, the chipActive
interrupt is issued to the host. This indicates device awake/ready status. See Table 7 for information on gSPI registers.
In Table 7, the following notation is used for register access:
■ R: Readable from host and CPU
■ W: Writable from host
■ U: Writable from CPU
Table 7. gSPI Registers
Address
Register
Word length
Bit
Access
Default
Description
0: 16-bit word length
1: 32-bit word length
0
R/W/U
0
0: Little endian
1: Big endian
Endianess
1
4
R/W/U
R/W/U
0
1
0: Normal mode. Sample on SPICLK rising edge, output
on falling edge.
1: High-speed mode. Sample and output on rising edge
High-speed mode
x0000
of SPICLK (default).
0: Interrupt active polarity is low.
1: Interrupt active polarity is high (default).
Interrupt polarity
Wake-up
5
7
0
R/W/U
R/W
1
0
1
A write of 1 denotes a wake-up command from host to
device. This will be followed by an F2 interrupt from the
gSPI device to host, indicating device awake status.
0: No status sent to host after a read/write.
1: Status sent to host after a read/write.
Status enable
R/W
x0002
x0003
0: Do not interrupt if status is sent.
1: Interrupt host even if status is sent.
Interrupt with status
Reserved
1
–
0
R/W
–
0
–
0
–
Requested data not available. Cleared by writing a 1 to
this location.
R/W
1
2
5
6
7
5
6
7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
F2/F3 FIFO underflow from the last read.
F2/F3 FIFO overflow from the last write.
F2 packet available
x0004
Interrupt register
Interrupt register
F3 packet available
F1 overflow from the last write.
F1 Interrupt
x0005
F2 Interrupt
F3 Interrupt
Interrupt enable
register
Particular interrupt is enabled if a corresponding bit is
set.
x0006, x0007
15:0
31:0
R/W/U
R
16'hE0E7
x0008 to x000B Status register
32'h0000 Same as status bit definitions
Document Number: 002-14796 Rev. *K
Page 22 of 101
CYPRESS [ CYPRESS ]
