PRELIMINARY
CYW43438
Figure 14. gSPI Signal Timing with Status (Response Delay = 0)
C S
W rite
S C LK
M O S I
CC3311
CC11
CC00
DD3311
DD11
DD00
SS3311
SS11
SS00
SS00
M IS O
C om m and 32 bits
W rite D ata 16*n bits
S tatus 32 bits
W rite-R ead
C S
S C LK
M O S I
M IS O
CC3311
CC00
SS3311
DD3311
DD11
DD00
R ead D ata 16*n bits
S tatus 32 bits
C om m and 32 bits
C S
R ead
S C LK
M O S I
M IS O
CC3311
CC00
SS3311
SS00
DD3311
DD11
DD00
C om m and 32 bits
R ead D ata 16*n bits
S tatus 32 bits
Table 6. gSPI Status Field Details
Bit Name
Description
The requested read data is not available.
0
Data not available
Underflow
1
FIFO underflow occurred due to current (F2, F3) read command.
FIFO overflow occurred due to current (F1, F2, F3) write command.
F2 channel interrupt.
2
Overflow
3
F2 interrupt
5
F2 RX ready
Reserved
F2 FIFO is ready to receive data (FIFO empty).
–
7
8
F2 packet available
F2 packet length
Packet is available/ready in F2 TX FIFO.
Length of packet available in F2 FIFO
9:19
4.2.2 gSPI Host-Device Handshake
To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN chip by writing to the wake-up WLAN
register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43438 is ready for data transfer. The
device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for
waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to
pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of the
interrupt and then take necessary actions.
Document Number: 002-14796 Rev. *K
Page 21 of 101
CYPRESS [ CYPRESS ]
